lowRISC is a complete open source SoC. The aim is to run Linux ‘well’, so not just a microcontroller; and to reach volume production. It started in summer 2014 as a non-profit project. Goals is teaching and research (cfr. RPi, but including the inside of the CPU), to support startups and innovation, and due to demand from the industry (because major vendors are so focused on mobile that the embedded industry is left a bit in the cold).
It’s a clean slate design, which is an opportunity to try out new ideas. Since technology scaling is slowing, there is more need to adapt the processor itself instead of just waiting a bit to get the performance.
RISC-V ISA is a research architecture from UCB. Has a 128-bit variant. It’s explicitly designed for extension with new instructions. 40 base instructions are enough to boot a system, but there are standard extensions for float, atomics, … It already has full toolchain support.
Creating open silicon has some challenges compared to software: huge fixed costs (mask sets, tooling, many steps), long development time, huge risk when it doesn’t work.
lowRISC is not a single-purpose solution but focuses on reusable components. It builds on existing Risc-V experience, adds some unique features (so it’s not competing against any other SoC).
Tagged memory associates metadata with each memory location (a few bits per 64-bit word). One use is to protect against control-flow hijacking (typical exploit using buffer overflows: they rely on overwriting a function pointer). A tag bit indicates if it is allowed to be used for control flow. Other uses: infinate watch/trace points, accurate debug/performance tools, lock bits for synchronisation, and whatever people can think of :-). The implementation is low overhead: the tags are stored separately in main memory, and added from a tag cache (similar to TLB) before L2.
Minion cores are very simple additional cores (also RISC-V) that are dedicated to I/O tasks. They make it possible to handle I/O in software rather than needing a separate peripheral for UART, SPI, I2C, … (maybe even USB, PCIe, …) And of course it can also be used to offload critical tasks. For instance, security tasks can run on it because the main OS cannot access them.
Minion cores have predictable timing, scratchpad instead of cache. I/O is through a shim which does simple parallel-serial shifting.
Security features are an essential part of the project. Tagged memory and minion cores to start with, but also secure boot, encrypted off-chip memory, virtualisation, etc. Basically known stuff. The difference that lowRISC makes is that it will be fully documented and auditable (open source, not under NDA) instead of a blob that you have to trust from the vendor.
The goal of the project is to be truly open source, so all development is in the open and there is also involvement from external contributors. But documentation needs to improve 🙂 There’s also a lot of software in the project, in tooling and OS.
Status: FPGA-based core with tagged memory; by the summer also minion cores. End of the year a dual-core test chip.
For the future, they’re thinking of adding GPU or DSP as well, but not immediately.
The EDA tooling and some of the interfaces (SDRAM PHY, probably also the controller) are not open source.