What tools are needed for FPGA development, and what is available in open source? Why is there so little in open source?
FPGA means logic design. FPGA consists of logic elements connected together with local and global interconnect. Each of these is configurable. Logic element is a look-up table and a register.
Every vendor provides their own toolchains for programming the FPGA, most of which you don’t need for small projects. These tools are generally closed source. The general flow is always the same.
- Analysis and synthesis: out of the schematics or the HDL, generate a netlist of logic functions and how they conect. Also drop any HDL that is not reachable, and more optimisation.
- Pack, place and route: map the netlist on the technology
- Assembly: create a bitstream
Timing analysis is needed to verify if the clock speed is met. Simulation is needed to verify functionality.
Analysis and synthesis tools
Icarus verilog is a GPL synthesis tool (with plugin exception). Mainly verilog but limited VHDL support. Generates simulation IL (VVP) and netlist. Mostly one-man show.
Odin II is used mostly in academia. It works mainly with netlists but also synthesizes HDL. Mostly used for ASIC synthesis.
Yosys is a newcomer. ISC license. Reads Verilog 2005 and BLIF netlists, outputs simplified Verilog or netlists. Does logic optimization using abc. Maps to ASIC, Xilinx 7-series and Lattice iCE40 (integration with VPR). Strong community.
Place and route
Map the netlist on the technology. Substeps: packing to fit into the larger logic array blocks, place the blocks, route the signals between the blocks.
Arachne PnR is specific for iCE40 and for Yosys. Shows that boundary between synthesis and place&route is not so sharp. Outputs a textual representation of the bitstream.
VPR is Versatile Placement and Routing. Uses FPGA models to allow flexibility to many FPGAs. Used extensively in research. Integrates in the commercial FPGA tools. What is missing to make it universal is models for the FPGAs.
The bitstream specifics are usually not documented by FPGA vendors, and you may need different bitstream format when programming over JTAG or loading from SPI flash, so just one tool.
IcePack is for iCE40. Takes output of Arachne PnR and transcribes into binary.
Putting it together
IceStorm project = Verilog to Bitstream, specific for Lattice iCE40. Yosys, Arachne, IcePack. In addition, IceProg for programming, and IceTime for timing analysis.
Simulation and verification
Simulation allows to specify triggers and constraints to be able to simulate it under varying conditions. It also allows you to look inside the block at internal signals, which is more difficult on actual hardware.
gHDL is a VHDL simulator. In translates VHDL to machine code with gcc/LLVM. Output is VCD (Value Change Dump, Verilog simulation format) or gHDL-specific format. Uses custom format for stimuli.
Icarus Verilog has a simulator as well. HDL is compiled to intermediate VVP code. vvp tool is used as an interpreter. Generates gtkWave output. Stimuli are specified in Verilog by instantiating the module under test and writing testbench code around it, Icarus just simulates the whole.
gtkwave is a waveform visualiser.
Why are FPGA tools so hard?
Bitstreams are undocumented.
Vendors have invested a lot in fine tuning their tools and algorithms, so they are afraid to release that.
IP vendors are afraid that a documented bitstream format will make it easier to reverse-engineer their secret sauce from a bitstream of from a SPI flash.
The person who has done the iCE40 bitstream reverse engineering is now working on Xilinx-7. There is also someone who looks at Altera, but that’s not public yet.
The open source tools are good for small designs. It’s likely that for large designs they would take ages to optimise.