RISC-V: Open Hardware for Your Open Source Software – Arun Thomas

This talk is a tour of the RISC-V ISA and ecosystem. The goal is to grow the community. There is RISC-V silicon now.

RISC-V is on open ISA specification. Implementations can be open or proprietary. No contract negotiations are needed. Its goal is to become the standard for all computing devices, from microcontrollers to supercomputers. It is targeted at research and education, but also commercial use. It started in 2010 as “common ISA” for research – x86 and ARM were too complicated, and have IP issues. In 2014 a frozen specification was published, the RISC-V Foundation continues the specification since 2015. The V is there because it is the 5th RISC ISA developed at UCB.

It’s a modular ISA: base instruction set (50 insns, fits on 1 sheet) and extensions can be added. 32, 64 and 128 bit versions exist. E.g. RV32I = 32-bit integer ISA. Standard extensions: M= integer divmul, A=atomic ops, F=float, D=double, G= “General purpose” (MMU etc.). There is also a compressed extension for better code density. Both user-level and privileged ISA are specified.

Many SoCs exist, for different use cases, written in a variety of HDLs, including Chisel, Bluespec SystemVerilog. Open source cores were developed while the ISA was developed. Several creators formed SiFive to design custom RISC-V chips for customers.

Rocket Chip is parameterized (cache hierarchy, #cores, …, single-issue or out-of-order) SoC generator. Written in Chisel HDL, can target C++ simulator, FPGA or ASIC Verilog. SiFive builds based on this. Freedom Everywhere is low cost, Freedom Unleashed is high-performance. HiFive1 is a devboard with silicon, $59, almost completely open source (SoC, PCB, …).

LowRISC aims to build a RPi-style low-cost devboard. They look at minion cores (for I/O offload) and tagged architectures (for security).

Shakti from IIT Madras with several low-to-high-end versions. RISC-V is the standard ISA for India.

More: PULPino (ETH Zurich), PicoRV32, many more.

The easiest way to customize is to tune the parameters of Rocket Chip. You can add an accelerator or an ISA extension. You can submit extensions for standardization.

There is a simulator, Spike, that acts as the golden model for the spec. Qemu support is ongoing but not fully upstream yet. RISCVEMU boots RISC-V/Linux in your browser. gem5 is a full-system simulator.

 

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